mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 4053 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 4941 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 4003 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2