mmDSCL1_OBUF_MEM_PWR_CTRL 4052 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0d9e
mmDSCL1_OBUF_MEM_PWR_CTRL 4940 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e76
mmDSCL1_OBUF_MEM_PWR_CTRL 4002 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e76