mmDSCL1_DSCL_MEM_PWR_STATUS 4048 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0d9c
mmDSCL1_DSCL_MEM_PWR_STATUS 4936 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e74
mmDSCL1_DSCL_MEM_PWR_STATUS 3998 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e74