mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 4047 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 4935 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 3997 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2