mmDSCL1_DSCL_MEM_PWR_CTRL 4046 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0d9b
mmDSCL1_DSCL_MEM_PWR_CTRL 4934 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e73
mmDSCL1_DSCL_MEM_PWR_CTRL 3996 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e73