mmDSCL1_DSCL_CONTROL_BASE_IDX 3995 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
mmDSCL1_DSCL_CONTROL_BASE_IDX 4883 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
mmDSCL1_DSCL_CONTROL_BASE_IDX 3945 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2