mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 3511 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 4301 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 3363 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2