mmDSCL0_SCL_COEF_RAM_TAP_SELECT 3510 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0c62
mmDSCL0_SCL_COEF_RAM_TAP_SELECT 4300 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cea
mmDSCL0_SCL_COEF_RAM_TAP_SELECT 3362 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cea