mmDSCL0_OBUF_MEM_PWR_CTRL 3576 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0c83
mmDSCL0_OBUF_MEM_PWR_CTRL 4366 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d0b
mmDSCL0_OBUF_MEM_PWR_CTRL 3428 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d0b