mmDSCL0_DSCL_MEM_PWR_STATUS 3572 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0c81
mmDSCL0_DSCL_MEM_PWR_STATUS 4362 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d09
mmDSCL0_DSCL_MEM_PWR_STATUS 3424 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d09