mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 3571 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 4361 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 3423 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2