mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 14347 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 12206 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2