mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 14299 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 12158 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2