mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 14034 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 11895 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121