mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 13819 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 11680 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2