mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 13771 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 11632 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2