mmDP_DTO1_PHASE_BASE_IDX  783 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
mmDP_DTO1_PHASE_BASE_IDX  583 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
mmDP_DTO1_PHASE_BASE_IDX  221 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
mmDP_DTO1_PHASE_BASE_IDX  233 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1