mmDPP_TOP3_DPP_CRC_VAL_R_G 4890 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x0f90
mmDPP_TOP3_DPP_CRC_VAL_R_G 5966 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
mmDPP_TOP3_DPP_CRC_VAL_R_G 5028 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108