mmDPP_TOP3_DPP_CRC_CTRL 4894 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x0f92
mmDPP_TOP3_DPP_CRC_CTRL 5970 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
mmDPP_TOP3_DPP_CRC_CTRL 5032 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a