mmDPP_TOP3_DPP_CONTROL_BASE_IDX 4887 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
mmDPP_TOP3_DPP_CONTROL_BASE_IDX 5963 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
mmDPP_TOP3_DPP_CONTROL_BASE_IDX 5025 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2