mmDPP_TOP2_HOST_READ_CONTROL 4421 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0e78
mmDPP_TOP2_HOST_READ_CONTROL 5398 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
mmDPP_TOP2_HOST_READ_CONTROL 4460 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0