mmDPP_TOP2_DPP_CRC_VAL_R_G 4415 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0e75
mmDPP_TOP2_DPP_CRC_VAL_R_G 5392 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
mmDPP_TOP2_DPP_CRC_VAL_R_G 4454 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d