mmDPP_TOP2_DPP_CONTROL 4411 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0e73
mmDPP_TOP2_DPP_CONTROL 5388 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
mmDPP_TOP2_DPP_CONTROL 4450 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b