mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 3947 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 4825 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 3887 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2