mmDPP_TOP1_HOST_READ_CONTROL 3946 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0d5d
mmDPP_TOP1_HOST_READ_CONTROL 4824 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
mmDPP_TOP1_HOST_READ_CONTROL 3886 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35