mmDPP_TOP1_DPP_CRC_VAL_R_G 3940 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0d5a
mmDPP_TOP1_DPP_CRC_VAL_R_G 4818 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
mmDPP_TOP1_DPP_CRC_VAL_R_G 3880 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32