mmDPP_TOP1_DPP_CRC_CTRL 3944 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0d5c
mmDPP_TOP1_DPP_CRC_CTRL 4822 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
mmDPP_TOP1_DPP_CRC_CTRL 3884 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34