mmDPP_TOP1_DPP_CONTROL 3936 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0d58
mmDPP_TOP1_DPP_CONTROL 4814 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
mmDPP_TOP1_DPP_CONTROL 3876 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30