mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 3471 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 4251 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 3313 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2