mmDPP_TOP0_HOST_READ_CONTROL 3470 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0c42
mmDPP_TOP0_HOST_READ_CONTROL 4250 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
mmDPP_TOP0_HOST_READ_CONTROL 3312 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca