mmDPP_TOP0_DPP_CRC_VAL_R_G 3464 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0c3f
mmDPP_TOP0_DPP_CRC_VAL_R_G 4244 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
mmDPP_TOP0_DPP_CRC_VAL_R_G 3306 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7