mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 3469 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 4249 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 3311 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2