mmDPP_TOP0_DPP_CONTROL 3460 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0c3d
mmDPP_TOP0_DPP_CONTROL 4240 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
mmDPP_TOP0_DPP_CONTROL 3302 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5