mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX  621 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX  259 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX  255 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1