mmDP5_DP_VID_TIMING_BASE_IDX 11633 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_VID_TIMING_BASE_IDX                                                                   2
mmDP5_DP_VID_TIMING_BASE_IDX 9914 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_VID_TIMING_BASE_IDX                                                                   2
mmDP5_DP_VID_TIMING_BASE_IDX 12597 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_VID_TIMING_BASE_IDX                                                                   2