mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 11627 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 9908 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 12591 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX                                                              2