mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 11645 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 9926 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 12609 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2