mmDP5_DP_SEC_CNTL1_BASE_IDX 11683 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_SEC_CNTL1_BASE_IDX                                                                    2
mmDP5_DP_SEC_CNTL1_BASE_IDX 9960 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_SEC_CNTL1_BASE_IDX                                                                    2
mmDP5_DP_SEC_CNTL1_BASE_IDX 12643 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_SEC_CNTL1_BASE_IDX                                                                    2