mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 10008 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 12691 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2