mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 11723 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 10000 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 12683 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2