mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 4642 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4fdd
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 5874 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4fdd
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 11722 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1e5b
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 9999 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2645
mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 12682 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2645