mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 9702 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 12367 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 11273 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2