mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 11365 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 9620 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 12285 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 11191 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2