mmDP4_DP_DPHY_PRBS_CNTL 4552 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
mmDP4_DP_DPHY_PRBS_CNTL 4542 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
mmDP4_DP_DPHY_PRBS_CNTL 5774 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
mmDP4_DP_DPHY_PRBS_CNTL 11374 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x1d33
mmDP4_DP_DPHY_PRBS_CNTL 3333 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4
mmDP4_DP_DPHY_PRBS_CNTL 3920 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x48d4
mmDP4_DP_DPHY_PRBS_CNTL 9629 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
mmDP4_DP_DPHY_PRBS_CNTL 12294 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
mmDP4_DP_DPHY_PRBS_CNTL 11200 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d