mmDP3_DP_SEC_CNTL5_BASE_IDX 9408 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
mmDP3_DP_SEC_CNTL5_BASE_IDX 12055 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
mmDP3_DP_SEC_CNTL5_BASE_IDX 10961 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2