mmDP3_DP_SEC_CNTL1_BASE_IDX 11115 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
mmDP3_DP_SEC_CNTL1_BASE_IDX 9340 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
mmDP3_DP_SEC_CNTL1_BASE_IDX 11987 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
mmDP3_DP_SEC_CNTL1_BASE_IDX 10893 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2