mmDP3_DP_SEC_CNTL1 4647 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
mmDP3_DP_SEC_CNTL1 4680 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
mmDP3_DP_SEC_CNTL1 5912 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
mmDP3_DP_SEC_CNTL1 11114 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP3_DP_SEC_CNTL1                                                                             0x1c42
mmDP3_DP_SEC_CNTL1 3307 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDP3_DP_SEC_CNTL1 0x45AB
mmDP3_DP_SEC_CNTL1 4015 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDP3_DP_SEC_CNTL1                                                      0x45ab
mmDP3_DP_SEC_CNTL1 9339 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP3_DP_SEC_CNTL1                                                                             0x242c
mmDP3_DP_SEC_CNTL1 11986 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP3_DP_SEC_CNTL1                                                                             0x242c
mmDP3_DP_SEC_CNTL1 10892 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP3_DP_SEC_CNTL1                                                                             0x242c