mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 10491 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 8668 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 11279 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 10185 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2