mmDP1_DP_SEC_CNTL1 4645 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
mmDP1_DP_SEC_CNTL1 4678 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
mmDP1_DP_SEC_CNTL1 5910 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
mmDP1_DP_SEC_CNTL1 10546 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP1_DP_SEC_CNTL1                                                                             0x1a42
mmDP1_DP_SEC_CNTL1 3203 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDP1_DP_SEC_CNTL1 0x1FAB
mmDP1_DP_SEC_CNTL1 4013 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDP1_DP_SEC_CNTL1                                                      0x1fab
mmDP1_DP_SEC_CNTL1 8719 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP1_DP_SEC_CNTL1                                                                             0x222c
mmDP1_DP_SEC_CNTL1 11330 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP1_DP_SEC_CNTL1                                                                             0x222c
mmDP1_DP_SEC_CNTL1 10236 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP1_DP_SEC_CNTL1                                                                             0x222c