mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 10563 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 8736 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 11347 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 10253 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2